module EXMEM(
    input clk,rst,
    input JALFlush_from_WB,   // flush IDEX regiater
    input PCScr_from_MEM,

    // control signals
    input branch_beq_from_EX, branch_bne_from_EX,      // work at MEM
    input JALFlush_from_EX,                            // work at WB

    input MemWrite_from_EX, MeMRead_from_EX,           // work at MEM   
    input RegWrite_from_EX, MeMtoReg_from_EX,          // work at WB
    
    // data
    input [31:0] JalAddr_from_EX,                 // work at WB    
    input [31:0] pc8_from_Ex,                     // work at WB    
    input [4:0]  rd_from_mux,                     // work at WB
    input  overflow_from_ALU,                     // work at WB
    input  zero_from_ALU,                         // work at MEM
    input [31:0] BranchAddr_from_EX,              // address of bne,beq,work at MEM
    input [31:0] Res_from_ALU,                    // work at MEM
    input [31:0] Data_rt_from_EX,                 // work at MEM, to Dcache
    
    // out     
    output reg beq_2_MEM, bne_2_MEM,                  // work at MEM
    output reg JALFlush_2_MEM,                          // work at WB

    output reg MemWrite_2_MEM, MeMRead_2_MEM,           // work at MEM   
    output reg RegWrite_2_MEM, MeMtoReg_2_MEM,          // work at WB

    output reg [31:0] JalAddr_2_MEM,                 // work at WB    
    output reg [31:0] pc8_2_MEM,                     // work at WB    
    output reg [4:0]  rd_2_MEM,                      // work at WB
    output reg  overflow_2_MEM,                      // work at WB
    output reg  zero_2_MEM,                          // work at MEM
    output reg [31:0] BranchAddr_2_MEM,              // address of bne,beq,work at MEM
    output reg [31:0] Res_2_MEM,                     // work at MEM
    output reg [31:0] Data_rt_2_MEM                  // work at MEM, to Dcache
);

always@(posedge clk or negedge rst)begin
    if(!rst)begin
        beq_2_MEM <= 1'b0; 
        bne_2_MEM <= 1'b0;                             // work at MEM
        JALFlush_2_MEM <= 1'b0;                          // work at WB

        MemWrite_2_MEM <= 1'b0; 
        MeMRead_2_MEM <= 1'b0;           // work at MEM   
        RegWrite_2_MEM <= 1'b0; 
        MeMtoReg_2_MEM <= 1'b0;          // work at WB

        JalAddr_2_MEM <= 32'd0;                 // work at WB    
        pc8_2_MEM <= 32'd0;                     // work at WB    
        rd_2_MEM <= 5'd0;                      // work at WB
        overflow_2_MEM <= 1'd0;                      // work at WB
        zero_2_MEM <= 1'd0;                          // work at MEM
        BranchAddr_2_MEM <= 32'd0;              // address of bne,beq,work at MEM
        Res_2_MEM <= 32'd0;                     // work at MEM
        Data_rt_2_MEM <= 32'd0;
    end
    else if(JALFlush_from_WB|PCScr_from_MEM)begin
        beq_2_MEM <= 1'b0; 
        bne_2_MEM <= 1'b0;                             // work at MEM
        JALFlush_2_MEM <= 1'b0;                          // work at WB

        MemWrite_2_MEM <= 1'b0; 
        MeMRead_2_MEM <= 1'b0;           // work at MEM   
        RegWrite_2_MEM <= 1'b0; 
        MeMtoReg_2_MEM <= 1'b0;          // work at WB

        JalAddr_2_MEM <= 32'd0;                 // work at WB    
        pc8_2_MEM <= 32'd0;                     // work at WB    
        rd_2_MEM <= 5'd0;                      // work at WB
        overflow_2_MEM <= 1'd0;                      // work at WB
        zero_2_MEM <= 1'd0;                          // work at MEM
        BranchAddr_2_MEM <= 32'd0;              // address of bne,beq,work at MEM
        Res_2_MEM <= 32'd0;                     // work at MEM
        Data_rt_2_MEM <= 32'd0;

    end else begin
        beq_2_MEM <= branch_beq_from_EX; 
        bne_2_MEM <= branch_bne_from_EX;                    // work at MEM
        JALFlush_2_MEM <= JALFlush_from_EX;                   // work at WB

        MemWrite_2_MEM <= MemWrite_from_EX; 
        MeMRead_2_MEM <= MeMRead_from_EX;                     // work at MEM   
        RegWrite_2_MEM <= RegWrite_from_EX; 
        MeMtoReg_2_MEM <= MeMtoReg_from_EX;                   // work at WB

        JalAddr_2_MEM <= JalAddr_from_EX;             // work at WB    
        pc8_2_MEM <= pc8_from_Ex;                     // work at WB    
        rd_2_MEM <= rd_from_mux;                      // work at WB
        overflow_2_MEM <= overflow_from_ALU;                  // work at WB
        zero_2_MEM <= zero_from_ALU;                          // work at MEM
        BranchAddr_2_MEM <= BranchAddr_from_EX;               // address of bne,beq,work at MEM
        Res_2_MEM <= Res_from_ALU;                     // work at MEM
        Data_rt_2_MEM <= Data_rt_from_EX;
    end
end
endmodule